Performance Evaluation of Superscalar Processor with Multi-Bank Register File Using SPEC2000

Recently, register files in highly parallel superscalar processors tend to have large chip area and many access ports. This trend causes problems with chip-size, access time and power consumption. As one of the approaches for solving these problems, researchers have proposed several methods using a multi-bank register file instead of multi-port register file. And we have proposed a method to achieve higher performance as compared with other methods. In this paper, we evaluate the effectiveness of our method by software simulation using SPECint2000. The results shows that a superscalar processor with our proposal method has only 1 % performance degradation in a cycle-based comparison with a conventional multi-port register file under the condition that each register bank in multi-bank register file has two read ports and two write ports. Additionally, our method keeps only 3 % performance degradation even if each bank register has only one port.